COA for GATE CS 2027: Weightage, Syllabus Changes & PYQs

Computer Organization and Architecture (COA) is worth about 8 marks per GATE CS paper, or roughly 7.8% of the 100-mark paper, and it is growing. We counted every COA question in all 23 official GATE CS papers from 2014 to 2026. COA averaged 7.8 marks and ranged from 4 to 13. It rose from 7.2 marks per paper before 2021 to 8.6 after, and every paper from 2024 to 2026 had 8 marks or more. It is the most numerical subject in the paper: since 2021, 55% of COA marks have come from numerical answer type (NAT) questions. Cache memory alone has been about 3 marks a paper. The 2027 syllabus wording has also changed, which this guide covers along with topic-by-topic numbers, five worked questions from past papers and a study order.

GATE CS 2027 COA Syllabus (and What Changed)

Computer Organization and Architecture is Section 3 of the official GATE 2027 CS syllabus. The official text reads:

• Instruction set and addressing modes
• Design of arithmetic and logic unit (ALU)
• Design of control unit: hardwired and microprogrammed
• Memory interfacing and hierarchy: performance, cache memory mapping
• I/O interface (interrupt and DMA)
• Instruction pipelining, pipeline hazards

The wording differs from the GATE 2026 CS syllabus, which listed "Machine instructions and addressing modes. ALU, data-path and control unit. Instruction pipelining, pipeline hazards. Memory hierarchy: cache, main memory and secondary storage; I/O interface (interrupt and DMA mode)." Comparing the two texts:

• Added explicitly: ALU design, hardwired and microprogrammed control unit design, and memory interfacing.
• No longer named: "main memory and secondary storage". Disk access-time questions came up 5 times between 2014 and 2026 (10 marks), the last in 2026 Set 1. The 2027 text no longer lists secondary storage, so treat these as lower priority. Don't skip them entirely, though, since "performance" in the memory hierarchy is still listed.
• Unchanged: pipelining and hazards, cache mapping, and interrupt and DMA-based I/O, which together carry most COA marks.

For the full CS syllabus, see our GATE CS syllabus page.

How Many Marks Does COA Carry in GATE CS?

The official question paper pattern fixes marks only for General Aptitude (15) and Engineering Mathematics (13). This is what COA carried in each paper:

What this means: COA has become one of the heavier technical subjects. The last six papers (2024 to 2026) averaged about 9.7 marks. COA questions are also mostly 2-mark (70 of 109), so each one you miss costs more. For how COA compares with other subjects, see our GATE CSE subject-wise weightage analysis.

Topic-Wise Weightage: Where COA Marks Come From

We grouped the 109 COA questions by syllabus heading, with the average marks per paper across all 23 papers:

Looking at individual topics, the most-asked across all 23 papers were cache numericals (26 questions, 44 marks, the single most-asked topic in COA), pipeline stages and throughput (10 questions, 18 marks) and instruction formats and opcode counting (11 questions, 18 marks).

Three patterns stand out:

1. Cache is a third of COA. Memory hierarchy and cache averaged 3.2 marks per paper in both periods, and 2026 had four cache questions across its two sets. If you prepare one thing thoroughly in COA, make it cache address breakdowns and hit-ratio calculations.
2. Pipelining is reliably numerical. 22 of the 27 pipelining and performance questions were NATs: speedup, time to process n instructions, and stall cycles. They are formula-driven and very scorable.
3. I/O has doubled, and control-unit design is now explicitly listed. Interrupt and DMA questions rose to 1.3 marks per paper. ALU and control-unit design have produced only 3 questions so far, but the 2027 syllabus now names hardwired and microprogrammed control explicitly, so cover the basics.

Question Types: COA Is the Most Numerical Subject

From 2021 to 2026, the 53 COA questions split into 27 NATs, 16 MCQs and 10 MSQs. By marks, NATs carried 47 of 86 (55%), which is the highest NAT share of any subject in our count. NATs have no negative marking but also no options to check against (official marking rules). Accuracy in calculation is what COA rewards:

• Note the given unit conventions (1 K = 2¹⁰ or 10³, G = 10⁹). GATE states them in the question, and they change the answer.
• Write the address breakdown (tag, index or set, offset) before you calculate anything.
• Check the rounding instruction in the question: "rounded off to two decimal places" is common.

Topic by Topic: What GATE Asks and How to Prepare

1. Memory Hierarchy and Cache

What gets asked: tag, index and offset sizes for direct-mapped, set-associative and fully associative caches; hit ratio and average memory access time; cache size from address mappings; replacement policies (LRU, FIFO); and memory interfacing with chips.

How to prepare: for every cache question, write: address bits = tag + index + offset, offset = log₂(block size), index = log₂(number of sets), and tag = the rest. For access time, be clear whether the levels are checked one after another or in parallel, because the question will say. Work through multi-level and write-policy variants after the basics.

Recent PYQs: direct-mapped cache with a 32-bit address (2026), 4 KB direct-mapped cache (2026, MSQ), cache and MMU together (2026, MSQ).

2. Pipelining and Performance

What gets asked: clock period from stage delays and latch delay, time for n instructions, speedup over non-pipelined execution, stalls from data and control hazards, forwarding, and CPI with stalls.

How to prepare: learn the core formulas. The clock period is the largest stage delay plus the latch delay. A k-stage pipeline needs (k + n − 1) cycles for n instructions. With stalls, CPI = 1 + (fraction stalled × stall cycles). Speedup is the old time per instruction divided by the new one, so include the clock change (worked example 1).

Recent PYQs: stalls from a memory-read EX stage (2026, NAT), RAW, WAR and WAW dependencies (2026).

3. Instructions and Addressing Modes

What gets asked: counting opcodes with expanding (variable-length) opcode formats, which addressing mode suits which data access, instruction encoding, and what belongs to the instruction set architecture.

How to prepare: for opcode questions, count in "encoding space". Each instruction type uses opcodes × 2^{operand bits} of the 2^{instruction length} total (worked example 4). For addressing modes, link each one to its typical use: immediate for constants, indexed for arrays, base-relative for records, indirect for pointers.

Recent PYQs: match addressing modes (2026), load–store ISA (2026), what is part of an ISA (2025, MSQ).

4. I/O: Interrupts, DMA and Disks

What gets asked: DMA transfer rates with cycle stealing, interrupt handling (vectored and non-vectored, priorities), interrupt overhead, and disk access time.

How to prepare: DMA rate = (fraction of cycles used) × clock rate × bytes per cycle, then convert bytes to bits if asked (worked example 5). For interrupts, learn the sequence of steps from the request to the return. Disk access-time questions are lower priority under the 2027 wording (see the syllabus section above), but a quick revision is cheap.

Recent PYQs: interrupt handling (2026), interrupts on a non-pipelined CPU (2025), disk at 15000 rpm (2026, NAT).

5. ALU, Datapath and Control Unit

What gets asked: so far, datapath control signals, Booth's multiplication and register-transfer sequences. Only 3 questions in 13 years.

How to prepare: the 2027 syllabus names ALU design and hardwired and microprogrammed control explicitly, so learn the basics. That means control word formats, horizontal versus vertical microprogramming, control memory size, and Booth's algorithm. Don't expect it to outweigh cache or pipelining.

Recent PYQs: partial datapath (2025, MSQ), Booth's multiplication (2025, NAT).

Worked Examples from Official GATE CS Papers

Each answer below matches the official answer key, as reproduced on the linked question page.

Example 1: Pipeline speedup with a slower clock (GATE CS 2026 Set 2, Q57, 2 marks, NAT)

Question: a non-pipelined unit at 1.6 GHz takes 5 cycles per instruction. The pipelined version runs at 1.2 GHz, aiming for 1 cycle per instruction, but 30% of instructions stall for 2 cycles. What is the speedup?

Solution: the old time per instruction is 5 ÷ 1.6 GHz = 3.125 ns. The new CPI is 1 + 0.3 × 2 = 1.6, so the new time is 1.6 ÷ 1.2 GHz ≈ 1.333 ns. Speedup = 3.125 ÷ 1.333 ≈ 2.34 (the official range is 2.3 to 2.4). If you forget the clock drop and use 5 ÷ 1.6, you get 3.125, which is wrong. Practise this question.

Example 2: Time for 1000 instructions (GATE CS 2025 Set 2, Q56, 2 marks, NAT)

Question: a 5-stage pipeline has stage delays of 180, 250, 150, 170 and 250 ns, and a 10 ns latch delay. How long do 1000 instructions take, in µs?

Solution: the clock period is the largest stage delay plus the latch: 250 + 10 = 260 ns. The number of cycles is k + n − 1 = 5 + 1000 − 1 = 1004. So the time is 1004 × 260 ns = 261,040 ns = 261.04 µs (the official range is 260.2 to 261.2). Practise this question.

Example 3: Largest possible cache (GATE CS 2026 Set 2, Q56, 2 marks, NAT)

Question: physical memory is 1 MB and byte-addressable. In a direct-mapped cache, address 0xA2C28 maps to block 176. What is the largest possible cache size?

Solution: the block index is a run of address bits just above the offset. 176 = 10110000₂. In binary, 0xA2C28 is 1010 0010 1100 0010 1000, and bits 13 to 6 read 10110000, so the offset is 6 bits (64-byte blocks). Bits 16, 15 and 14 are all 0, so the index can extend up to bit 16 and still equal 176. That gives an 11-bit index. Bit 17 is 1, which stops it there. Cache size = 2¹¹ blocks × 2⁶ bytes = 2¹⁷ bytes = 128 KB. Practise this question.

Example 4: Expanding opcodes (GATE CS 2026 Set 2, Q44, 2 marks)

Question: instructions are 16 bits wide with 16 registers (4 bits each). M-type has 2 registers and a 6-bit immediate. R-type has 3 registers. C-type has 1 register and a 6-bit offset. With 2 M-type and 7 R-type opcodes, what is the maximum number of C-type opcodes?

Solution: M-type operands take 14 bits, so its 2 opcodes use 2 × 2¹⁴ encodings. R-type operands take 12 bits, so its 7 opcodes use 7 × 2¹². C-type operands take 10 bits, so X opcodes use X × 2¹⁰. The total must be at most 2¹⁶. Dividing by 2¹⁰ gives 32 + 28 + X ≤ 64, so X ≤ 4. Practise this question.

Example 5: DMA with cycle stealing (GATE CS 2024 Set 2, Q11, 1 mark)

Question: a 4 MHz processor has a DMA controller that moves 8 bytes per cycle, using 1% of processor cycles. What is the transfer rate in bits per second?

Solution: DMA gets 0.01 × 4 × 10⁶ = 40,000 cycles per second. 40,000 × 8 bytes = 320,000 bytes per second, which is 2,560,000 bits per second. A common mistake is to stop at bytes. Practise this question.

Study Order and Time Plan

COA takes roughly 4 to 5 weeks at 2 hours a day. Study Digital Logic first, because number representation and circuits come up in COA too.

1. Instructions and addressing modes (4 days): ISA basics and expanding opcodes.
2. ALU, datapath and control unit (3–4 days): now explicitly in the syllabus. Cover hardwired and microprogrammed control.
3. Memory hierarchy and cache (8–9 days): the biggest topic. Do address breakdowns daily.
4. Pipelining and hazards (6–7 days): formulas first, then stalls and forwarding.
5. I/O, interrupts and DMA (3 days), plus a quick pass on disk timing.
6. PYQ sweep (3–4 days): all 109 COA questions from 2014 to 2026 on the GATE CS PYQ archive.

For where COA fits among all the subjects, see the GATE CSE 2027 month-by-month study plan.

Best Books for GATE CS COA

For other subjects, see our best books for GATE CSE 2027. The full course, covering all subjects with lectures and mock tests, is on the GATE CS course page.

Common Mistakes in GATE COA

• Leaving out the clock change when computing pipeline speedup (Example 1).
• Using n × k cycles instead of k + n − 1 for a pipeline with no stalls.
• Ignoring the question's unit convention for K, M and G.
• Stopping at bytes when the question asks for bits (Example 5).
• Assuming the cache levels are accessed in parallel when the question describes them as one after another, or the other way round.

Key Takeaways

• COA averaged 7.8 marks per paper (7.8% of the paper) across 23 official GATE CS papers (2014–2026), rising to 8.6 since 2021 and about 9.7 in 2024–2026.
• Cache is about a third of COA (74 marks overall), and pipelining is next (49 marks).
• NATs carried 55% of COA marks from 2021 to 2026, the highest share of any subject.
• The 2027 wording adds ALU and control-unit design and memory interfacing, and no longer names secondary storage.

Frequently Asked Questions

How many marks does COA carry in GATE CS?

The official pattern does not fix marks per CS subject. Across all 23 official GATE CS papers from 2014 to 2026, COA averaged 7.8 marks per paper, which is 7.8% of the 100-mark paper, with a range of 4 to 13. Since 2021 it has averaged 8.6.

Which COA topics are most important for GATE CS 2027?

Cache memory (about 3.2 marks per paper) and pipelining (about 2.2) carry most of the marks. Instruction formats and I/O come next. Control-unit design is now explicitly listed in the 2027 syllabus.

Has the COA syllabus changed for GATE 2027?

Yes, the wording has changed. The 2027 syllabus explicitly lists ALU design, hardwired and microprogrammed control unit design, and memory interfacing. It no longer names "main memory and secondary storage", which the 2026 syllabus did. Pipelining, cache mapping and interrupt and DMA I/O remain.

Which book is best for COA for GATE CS?

Computer Organization by Hamacher, Vranesic and Zaky is the primary text. Add Patterson and Hennessy for pipelining and caches, and Mano for microprogrammed control.

Is COA hard in GATE CS?

COA questions are mostly numerical, but formula-driven. Success Tracker rates 16 of the 109 questions as hard. With a fixed method for cache, pipeline and DMA calculations, it is one of the more scorable subjects.

Where can I practise GATE CS COA PYQs?

Every GATE CS question from 2014 to 2026 is free on Success Tracker's GATE CS PYQ archive, with the official answer and a worked solution.

Next in This Series

• Programming and Data Structures for GATE CS 2027
• Operating System for GATE CS 2027
• Algorithms for GATE CS 2027
• GATE CSE subject-wise weightage
• GATE CS 2027 complete guide

Sources

• GATE 2027 CS Syllabus (PDF), IIT Madras: Section 3, Computer Organization and Architecture
• GATE 2026 CS Syllabus (PDF), IIT Guwahati: Section 3 (for the comparison)
• GATE 2027 Question Paper Pattern, IIT Madras: marks distribution and negative marking
• Official GATE CS question papers and answer keys, 2014–2026 (23 papers), as reproduced on Success Tracker. Weightage figures are The ML Hub's own count, done on 25 October 2026.